Programmable clock manager for a programmable logic device that can implement delay-locked loop functions
US6043677A · kind A · utility
42Cited by
14References
9Claims
0Family size
Assignee
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Key dates
| Filing date | Oct 15, 1997 |
| Grant date | Mar 28, 2000 |
| Priority date | — |
| Expiry date | Oct 15, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0814
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmable logic device (PLD), such as a field programmable gate array (FPGA), has a programmable clock manager (PCM) that converts an input clock into at least one output clock and the PCM can perform one or more delay-locked loop (DLL) functions. In one embodiment, the DLL functions include clock delay, duty-cycle adjustment, and clock doubling, where duty-cycle adjustment can optionally be applied independently to the doubled clock cycles.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.