Programmable universal test interface for testing memories with different test methodologies
US6044481A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 18, 1998 |
| Grant date | Mar 28, 2000 |
| Priority date | — |
| Expiry date | Jun 18, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/48
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A programmable memory test interface for testing a memory device is disclosed. The interface includes a plurality of programmable input pins and output pins. The interface also includes a logic interfacing means for connecting external signals to the plurality of programmable input pins and output pins. The external signals are processed by the logic interfacing means and then communicated to a plurality of memory connection pins that couple up to the memory device. The logic component means is capable of being configured in accordance with one or more memory testing methodologies including a serial built-in-self-test (BIST), a parallel built-in-self-test (BIST), a parallel test, a serial test, and a scan test. The configuring is performed by selectively interconnecting selected ones of the plurality of input pins and output pins to the external signals that drive the logic interface means in a test mode that operates in one or more memory testing methodologies or a mission mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.