Semiconductor device manufacturing method including ashing process
US6044850A · kind A · utility
5Cited by
7References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 30, 1997 |
| Grant date | Apr 4, 2000 |
| Priority date | — |
| Expiry date | Oct 30, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02071
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Ashing process of a resist pattern used in a semiconductor device manufacturing method is conducted by exposing the resist, the wirings, and their peripheral regions to a first atmosphere which includes a first product obtained by plasmanizing a gas containing water at a rate of more than 30 flow rate %, and placing the resist in a second atmosphere which includes a second product obtained by plasmanizing an oxygen mixed gas which contains an oxygen gas as a principal component before or after or before and after the exposing step.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.