Sealing electronic packages containing bumped hybrids
US6045030A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 13, 1997 |
| Grant date | Apr 4, 2000 |
| Priority date | — |
| Expiry date | Mar 13, 2017 |
Classification
- Technology area (CPC B)Performing Operations; Transporting
- CPC primaryB23K2101/40
- WIPO fieldMachine tools
- WIPO sectorMechanical engineering
Abstract
A method of packaging hybrid wafers or die that are interconnected using soft metal bumps, such as indium, in a sealed ceramic package. The present invention passivates the hybrid die that are to be interconnected by way of the bumps, so that the metal in the bumps (indium) does not wet the surface of the hybrid die when the ceramic package is sealed at high temperature. Vias are formed in the passivated surfaces to expose underlying contact areas. Bumps are then formed on the contact areas, and the bumped and passivated hybrid die are electrically interconnected. The ceramic package containing the electrically interconnected hybrid die is processed at a temperature above the melting temperature of the bumps to attach a ceramic cover to the ceramic package. The method is performed at a temperature well in excess of the melting temperature of the bumps (.about.155.degree. Celsius for indium), typically on the order of 325.degree. Celsius. The surface tension of the indium maintains the bump structure and electrical contact between the two hybrid die. The present invention may also be employed with flip chip and multi-chip module ceramic packages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.