Method and apparatus for optimizing memory performance with opportunistic refreshing
US6046952A · kind A · utility
12Cited by
1References
35Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 4, 1998 |
| Grant date | Apr 4, 2000 |
| Priority date | — |
| Expiry date | Dec 4, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/406
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller for a dynamic random access memory having counters for each chip select in the memory. The counters are incremented at a fixed interval. Programmable threshold values are provided which, when compared with the counters, indicate to the memory controller when a refresh should be opportunistically attempted and when a refresh is urgently required. The memory controller then either attempts to find an idle cycle to send the opportunistic refresh or blocks memory accesses to create a window for an urgently needed refresh. Once a refresh is sent to the memory, the appropriate counter is decremented accordingly.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.