Speculative direct memory access transfer between slave devices and memory
US6047336A · kind A · utility
8Cited by
11References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 16, 1998 |
| Grant date | Apr 4, 2000 |
| Priority date | — |
| Expiry date | Mar 16, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A DMA Controller, in response to a data transfer request from a slave device, initiates a memory transfer cycle and informs the slave device when the data transfer has completed. In order to avoid dead clock cycles on internal bus(es), the DMA Controller initiates a speculative data transfer cycle after the notification. The DMA Controller aborts the speculative data transfer cycle if the slave device does not request another data transfer within a predetermined time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.