Computer system which performs intelligent byte slicing on a multi-byte wide bus
US6047350A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 11, 1997 |
| Grant date | Apr 4, 2000 |
| Priority date | — |
| Expiry date | Dec 11, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4027
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A computer system optimized for real-time applications which provides increased performance over current computer architectures. The system includes a standard local system bus or expansion bus, such as the PCI bus, and may also include a dedicated real-time bus or multimedia bus. Various multimedia devices are coupled to one or more of the expansion bus and/or the multimedia bus. The computer system includes byte slicing logic coupled to one or more of the expansion bus and/or the multimedia bus which operates to allow different data streams to use different byte channels simultaneously. Thus the byte sliced multimedia bus allows different peripherals to share the bus simultaneously. The byte slicing logic thus may assign one data stream to a subset of the total byte lanes on the multimedia bus, and fill the unused byte lanes with another data stream. The computer system of the present invention thus provides much greater performance for real-time applications than prior systems.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.