Processor with short set-up and hold times for bus signals
US6047382A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 7, 1998 |
| Grant date | Apr 4, 2000 |
| Priority date | — |
| Expiry date | Oct 7, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0012
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor includes a system bus interface that permits short set-up and hold times for bus signals including loop-back signals. Loop-back signals are transferred from an input cell in the interface to a target I/O cell in the interface without resynchronizing the loop-back signal with the processor clock. Accordingly, set-up and hold times for the loop-back signal need only be sufficient to allow for jitter or uncompensated delay in the bus clock signal at the target I/O cell. The processing core provides valid signals that might be required for generating an output signal from the target cell. The core avoids changing those signals near triggering edges of the bus clock signal to prevent the signals from changing before the target I/O cell uses the required signals. Typically, the loop-back signal determines whether I/O cell is enabled for output and is also used at the edge of the bus clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.