MOSFET device to reduce gate-width without increasing JFET resistance
US6049104A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 28, 1997 |
| Grant date | Apr 11, 2000 |
| Priority date | — |
| Expiry date | Nov 28, 2017 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/944
Abstract
The present invention discloses a method for fabricating a MOSFET device supported on a substrate. The method includes the steps of (a) growing an oxide layer on the substrate followed by depositing a polysilicon layer and applying a gate mask for performing an undercutting dry etch for patterning a plurality of polysilicon gates with a gate width narrower than a width of the gate mask; (b) applying the gate mask as body implant blocking mask for implanting a body dopant followed by removing the gate mask and carrying out a body diffusion for forming body regions; (c) applying a source blocking mask for implanting a source dopant to form a plurality of source regions; (d) forming an overlying insulation layer covering the MOSFET device followed by applying a dry oxide etch with a contact mask as a second mask to open a plurality of contact openings there through then removing the contact mask; (e) performing a high temperature reflow process for the overlying insulation layer and for driving the source regions into designed junction depths; (f) depositing a metal layer followed by applying a metal mask for patterning the metal layer to define a plurality of metal segments.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.