Bitline bias circuit for non-volatile memory devices
US6049491A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 23, 1999 |
| Grant date | Apr 11, 2000 |
| Priority date | — |
| Expiry date | Feb 23, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bitline bias circuit, particularly for non-volatile memories, is disclosed. The bitline bias circuit includes an inverting stage which drives a first cascode transistor for biasing a selected bitline. A terminal of the first cascode transistor is fed back as an input to the inverting stage so as to form a first feedback loop. The bitline bias circuit further includes a second cascode transistor having a control terminal driven by the output of the inverting stage and a terminal which is fed back as an input to the inverting stage, thereby forming a second feedback loop. The feedback loops eliminate oscillations appearing on internal signals so as to reduce memory cell read cycle times.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.