Method and apparatus for checking cache coherency in a computer architecture
US6049851A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 14, 1994 |
| Grant date | Apr 11, 2000 |
| Priority date | — |
| Expiry date | Feb 14, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0831
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A double cache snoop mechanism in uniprocessor computer systems having a cache and coherent I/O and multiprocessor computer systems reduces the number of cycles that a processor is stalled during a coherency check. The snoop mechanism splits each coherency check, such that a read-only check is first sent to the cache subsystem., and a read-write check is sent thereafter only if there is a cache hit during the read-only check, and there is the need to modify the cache. Average processor pipeline stall time is reduced even though a cache hit results in an additional coherency check because most coherency checks do not result in a cache hit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.