Test system for integrated circuits using a single memory for both the parallel and scan modes of testing
US6049901A · kind A · utility
Inventors
Key dates
| Filing date | Sep 16, 1997 |
| Grant date | Apr 11, 2000 |
| Priority date | — |
| Expiry date | Sep 16, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31919
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A semiconductor test system has a scan test mode and a parallel test mode. A single memory using substantially all of its storage space stores a) parallel test vectors for use during the parallel test mode, and b) parallel test vectors and scan test vectors for use during the scan test mode. A switch is used to change from the parallel test mode to the scan test mode. A pattern generator coupled to the single memory manipulates the parallel test vectors used during the parallel test mode and the parallel and scan test vectors used during the scan test mode. The speed of the scan test mode is increased by interleaving the memory and reading test vectors out of the memory in parallel. Processing time is further decreased by creating multiple scan chains and applying them to multiple pins of the device under test (DUT). Lastly, the clock speed of the bus feeding scan chain data to the pins of the DUT is increased by multiplexing the scan chain data being transferred to the bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.