Chip and board stress relief interposer
US6050832A · kind A · utility
128Cited by
30References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 7, 1998 |
| Grant date | Apr 18, 2000 |
| Priority date | — |
| Expiry date | Aug 7, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An interposer structure permits a differential transverse displacement of contact pads on opposite sides of the interposer to reduce thermal stresses when the interposer is bonded to contact pads of a chip and a substrate with different thermal coefficients of expansion. The effective elasticity of the interposer between top and bottom contact pads of the interposer is facilitated by perforations which define flap-like regions. A flexible trace couples top contact pads to bottom contact pads through a via while permitting substantial transverse relative displacement of the top and bottom contact pads in flap-like regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.