Method for fabricating a capacitor of a DRAM with an HSG layer

US6051464A · kind A · utility

Assignee

• United Integrated Circuits Corp · JP

Inventors

• Weng-Yi Chen · Hengshan, TW
• Kuen-Chu Chen · 東區, TW

Key dates

• Filing date: Dec 4, 1998
• Grant date: Apr 18, 2000
• Expiry date: Dec 4, 2018

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D1/716

Abstract

A method for fabricating a capacitor including a storage capacitor of a dynamic random access memory (DRAM) starts with forming a dielectric layer and then a mask on a provided substrate, wherein the provided substrate contains a pre-formed field effect transistor (FET). By patterning the dielectric layer, a contact window is formed to expose the source/drain regions on the provided substrate. Then, a conducting layer is formed to cover the mask and fill the contact window, wherein the conducting layer is electrically connected to the source/drain region. A hemispherical-grained silicon (HSG) layer is formed on the conducting layer, wherein the silicon grains are respectively surrounded by spacers formed in a follow-up process. The HSG layer and a portion of the conducting layer are removed by performing an anisotropic etching process that uses the spacers as masks. The remains of the conducting layer, a multi-micro-cylinder structure, serves as the storage electrode of a capacitor. A dielectric layer and then, another conducting layer are formed on the multi-micro-cylinder structure after the spacers are removed.