Method of forming a semiconductor structure with uniform threshold voltage and punch-through tolerance
US6051468A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 15, 1997 |
| Grant date | Apr 18, 2000 |
| Priority date | — |
| Expiry date | Sep 15, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/26586
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A MOSFET (Metal Oxide Semiconductor Field Effect Transistors) structure is fabricated by first forming a plurality of trenches in a semiconductor substrate which includes a major surface. The trenches are then lined with insulating material and thereafter filled with conductive material. The process of filling the conductive material in the trenches normally involves an over-etching step for preventing any residual material remaining on the major surface. The over-etching of the conductive material in the trenches alters the evenness of the major surface and presents a problem for the later angular ion implantation of the source layer. As a consequence, the source layer formed includes asymmetrical source segments which generates nonuniform threshold voltage and punch-through tolerance in the MOSFET structure. The inventive method provides a spacer layer to compensate for the unevenness of the major surface. Prior to the ion implantation of the source layer, the spacer layer is formed above the conductive material and surrounding the insulating material adjacent the major surface. Source segments thus formed are symmetrical in shape enabling the fabricated MOSFET structure to opera…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.