Method of forming wirings
US6051490A · kind A · utility
7Cited by
33References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 21, 1997 |
| Grant date | Apr 18, 2000 |
| Priority date | — |
| Expiry date | Nov 21, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming wirings which includes forming a film of a silicon-containing metal layer at a high temperature on an underlying metal, thereby forming a silicon alloy layer which includes the underlying metal and the silicon-containing metal during film formation. In a case of forming wirings by a silicon-containing metal layer, occurrence of Si nodules can be eliminated to obtain wirings of high reliability.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.