Method of forming interconnections in an integrated circuit
US6051884A · kind A · utility
25Cited by
6References
17Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 17, 1998 |
| Grant date | Apr 18, 2000 |
| Priority date | — |
| Expiry date | Jul 17, 2018 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/921
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The invention provides a method for producing wiring and contacts in an integrated circuit including the steps of forming insulated gate components on a semiconductor substrate; applying a photo-reducible dielectric layer to cover the substrate; etching holes and forming contacts; photo-reducing the dielectric to increase its conductivity; covering the resulting structure with an interconnect layer; etching the interconnect layer to define wiring in electrical contact with the contacts; and oxidizing the dielectric to reduce its conductivity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.