CMOS delay circuit
US6052003A · kind A · utility
7Cited by
13References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 30, 1998 |
| Grant date | Apr 18, 2000 |
| Priority date | — |
| Expiry date | Apr 30, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/133
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A CMOS delay circuit for differential signals is provided. By adjusting the amplitude of clamping voltages, the delay period may be adjusted to a desired level. By using a single constant current source to charge both output nodes, current consumption is reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.