System for asserting burst termination signal and burst complete signal one cycle prior to and during last cycle in fixed length burst transfers
US6052745A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 12, 1998 |
| Grant date | Apr 18, 2000 |
| Priority date | — |
| Expiry date | Jun 12, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a method and system for fixed length bursts of data on a bus within a data processing system. The method and system in accordance with the present invention provides a burst transfer protocol which includes the providing of length information of a fixed length burst of data on a signal from at least one master device to at least one slave device when the at least one master device requests the fixed length burst of data. It also includes the asserting of a burst termination signal by the at least one slave device one cycle prior to a last cycle in the fixed length burst, and the asserting of a burst complete signal during the last cycle in the fixed length burst for a write burst, or one cycle prior to the last cycle in the fixed length burst for a read burst, based on the value of the signal. This burst transfer protocol enables burst transfers of a maximum length to be performed across a local bus between a master and a slave without dead cycle penalties after the transfer. This improves the efficiency and performance of data throughput across the local bus without the need to increase the frequency. The present invention requires no new signals and…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.