Method and apparatus for ECC bus protection in a computer system with non-parity memory
US6052818A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 27, 1998 |
| Grant date | Apr 18, 2000 |
| Priority date | — |
| Expiry date | Feb 27, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1048
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method in which ECC bus protection capability can be generated on a memory card in conjunction with a computer system with a built-in ECC capability to reduce data transmission errors. Data generated by the system is transmitted to the card and stored in DRAMs. On a read cycle, the card generates a set of checkbits which are sent to the system on a checkbit bus. The system generates a set of checkbits from the data read from the memory card and compares these checkbits with those received from the memory card. A mismatch indicates transmission error on the bus(s) during a read cycle. Any correctable error is corrected. Data is invalidated if an uncorrectable error is detected. In another embodiment checkbits generated by the system during a write cycle are transmitted to the card an checkbits are generated by the card. These two sets of checkbits are compared and if there is a mismatch data is either flagged as bad or corrected. Furthermore, in one embodiment, if the memory card does "not know" in advance the type of ECC or H-matrix code resident in the computer system, the card has the capability to determine what H-matrix code is resident and set up a correspondi…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.