Method of manufacturing a silicon carbide vertical MOSFET
US6054352A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 20, 1998 |
| Grant date | Apr 25, 2000 |
| Priority date | — |
| Expiry date | Feb 20, 2018 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/931
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a silicon carbide vertical MOSFET is presented which includes: providing a first conductivity type silicon carbide substrate; a first conductivity type drift layer comprising silicon carbide which is formed on the first conductivity type silicon carbide substrate; a second conductivity type base region formed in a selected region of a surface layer of the first conductivity type drift layer; a first conductivity type source region formed in a selected region of the second conductivity type base region; a gate electrode layer formed on a gate insulating film over at least a part of an exposed surface portion of the second conductivity type base region interposed between the first conductivity type source region and the first conductivity type drift layer; a source electrode formed in contact with surfaces of the first conductivity type source region and the second conductivity type base region; and a drain electrode formed on a rear surface of the silicon carbide substrate. In the manufacture of the vertical MOSFET, the first conductivity type source region is formed by ion implantation of first conductivity type impurities using a first mask, and the secon…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.