Single polysilicon flash EEPROM with low positive programming and erasing voltage and small cell size
US6054732A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 30, 1998 |
| Grant date | Apr 25, 2000 |
| Priority date | — |
| Expiry date | Jan 30, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/10
Abstract
A single polysilicon memory cell (10) provides a positive low programming and erase voltage together with a small cell size and includes P substrate (12) and P-well (14) formed within P substrate (12). NMOS transistor (16) is formed within P-well (14). N.sup.+ control gate (26) is formed in P-well (14) and includes punch-through implant region (26). NMOS transistor (16) and N.sup.+ control gate (26) have in common electrically isolated polysilicon gate (22, 32) for operating as a floating gate in common with NMOS transistor (16) and N.sup.+ control gate (26). N.sup.+ control gate (26) includes P-channel punch-through implant (34) for increasing the capacitive coupling ratio. This improves programming and erasing efficiency within single polysilicon memory cell (10).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.