Sensing circuitry for reading and verifying the contents of electrically programmable/erasable non-volatile memory cells
US6055187A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 9, 1998 |
| Grant date | Apr 25, 2000 |
| Priority date | — |
| Expiry date | Dec 9, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A sense amplifier circuit for reading and verifying the contents of non-volatile memory cells in a semiconductor integrated device including a memory matrix of electrically programmable and erasable cells. The circuit includes a sense amplifier which has a first input connected to a reference load column incorporating a reference cell, and a second input connected to a second matrix load column incorporating a cell of the memory matrix. The circuit also includes a small matrix of reference cells connected, in parallel with one another, in the reference load column. Also provided is a double current mirror having a first mirror column which is connected to a node in the reference load column connected to the first input, and a second mirror column coupled to the second matrix load column to locally replicate, on the second mirror column, the electric potential at the node during a load equalizing step.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.