Adder circuit and method therefor
US6055557A · kind A · utility
7Cited by
18References
19Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Jan 8, 1997 |
| Grant date | Apr 25, 2000 |
| Priority date | — |
| Expiry date | Jan 8, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/505
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An adder (300) generates encoded outputs to conserve power. In particular, the adder provides "B2" encoded outputs which only drive one bit per every two bits at a time on conductive lines in a data processing system. A binary input is encoded by an encoder (800, 304) to generate a plurality of bits. The plurality of bits are concatenated to form a plurality of sum values. A portion of the plurality of sum values are then selectively output in response to a logic value of a carry kill signal, a carry generate signal, and a carry propagate signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.