Technique for reducing latency of inter-reference ordering using commit signals in a multiprocessor system having shared caches
US6055605A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 24, 1997 |
| Grant date | Apr 25, 2000 |
| Priority date | — |
| Expiry date | Oct 24, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/084
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A technique reduces the latency of inter-reference ordering between sets of memory reference operations in a multiprocessor system having a shared memory that is distributed among a plurality of processors that share a cache. According to the technique, each processor sharing a cache inherits a commit-signal that is generated by control logic of the multiprocessor system in response to a memory reference operation issued by another processor sharing that cache. The commit-signal facilitates serialization among the processors and shared memory entities of the multiprocessor system by indicating the apparent completion of the memory reference operation to those entities of the system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.