Madhumitra Sharma
18Patents
16h-index
9Co-inventors
60Inventor score
Filing activity: Oct 24, 1997 → Aug 20, 2001
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6055605A | Technique for reducing latency of inter-reference ordering using commit signals in a multiprocessor system having shared caches | Physics | 103 | Expired |
| US6209065A | Mechanism for optimizing generation of commit-signals in a distributed shared-memory system | Physics | 95 | Expired |
| US6108737A | Method and apparatus for reducing latency of inter-reference ordering in a multiprocessor system | Physics | 92 | Expired |
| US6014690A | Employing multiple channels for deadlock avoidance in a cache coherency protocol | Physics | 78 | Expired |
| US6085276A | Multi-processor computer system having a data switch with simultaneous insertion buffers for eliminating arbitration interdependencies | Physics | 76 | Expired |
| US6088771A | Mechanism for reducing latency of memory barrier operations on a multiprocessor system | Physics | 71 | Expired |
| US6085263A | Method and apparatus for employing commit-signals and prefetching to maintain inter-reference ordering in a high-performance I/O processor | Physics | 71 | Expired |
| US6279084A | Shadow commands to optimize sequencing of requests in a switch-based multi-processor system | Physics | 64 | Expired |
| US6101420A | Method and apparatus for disambiguating change-to-dirty commands in a switch based multi-processing system with coarse directories | Physics | 62 | Expired |
| US6286090A | Mechanism for selectively imposing interference order between page-table fetches and corresponding data fetches | Physics | 48 | Expired |
| US6154816A | Low occupancy protocol for managing concurrent transactions with dependencies | Physics | 45 | Expired |
| US6094686A | Multi-processor system for transferring data without incurring deadlock using hierarchical virtual channels | Physics | 42 | Expired |
| US6249520A | High-performance non-blocking switch with multiple channel ordering constraints | Physics | 39 | Expired |
| US6122714A | Order supporting mechanisms for use in a switch-based multi-processor system | Physics | 25 | Expired |
| US6801986B2 | Livelock prevention by delaying surrender of ownership upon intervening ownership request during load locked / store conditional atomic memory operation | Physics | 21 | Expired |
| US6202126A | Victimization of clean data blocks | Physics | 17 | Expired |
| US6961825B2 | Cache coherency mechanism using arbitration masks | Electricity | 4 | Expired |
| US6904465B2 | Low latency inter-reference ordering in a multiple processor system employing a multiple-level inter-node switch | Electricity | 0 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.