Microprocessor with a nestable delayed branch instruction without branch related pipeline interlocks
US6055628A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 23, 1998 |
| Grant date | Apr 25, 2000 |
| Priority date | — |
| Expiry date | Jan 23, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3853
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microprocessor 1 has an instruction fetch/decode unit 10a-c, a plurality of execution units, including an arithmetic and load/store unit D1, a multiplier M1, an ALU/shifter unit S1, an arithmetic logic unit ("ALU") L1, a shared multiport register file 20a from which data are read and to which data are written, and a memory 22. These units form an instruction execution pipeline that operates without interlocks so that nestable delayed branch instructions are provided. The control circuitry for the instruction execution pipeline is operable to begin processing a second branch instruction having a second target address on a pipeline phase immediately after beginning processing of a first branch instruction having a first target address. Furthermore, the control circuitry has no interlock or delay circuitry to condition processing of the second branch instruction based on processing of the first branch instruction, therefore the program counter circuitry receives the second target address on a pipeline phase immediately after receiving the first target address regardless of whether the first branch is taken or not. Thus, one instruction may be executed from the first target branch ad…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.