Laurence R. Simar
22Patents
9h-index
14Co-inventors
72Inventor score
Filing activity: Sep 28, 1990 → Feb 22, 2019
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6182203A | Microprocessor | Physics | 96 | Expired |
| US5390304A | Method and apparatus for processing block instructions in a data processor | Physics | 41 | Expired |
| US5826101A | Data processing device having split-mode DMA channel | Physics | 32 | Expired |
| US6374346B1 | Processor with conditional execution of every instruction | Physics | 31 | Expired |
| US5305446A | Processing devices with improved addressing capabilities, systems and methods | Physics | 28 | Expired |
| US6625719B2 | Processing devices with improved addressing capabilities systems and methods | Physics | 19 | Expired |
| US7886255B2 | Method for design of programmable data processors | Physics | 14 | Active |
| US5410652A | Data communication control by arbitrating for a data transfer control token with facilities for halting a data transfer by maintaining possession of the token | Physics | 11 | Expired |
| US5751991A | Processing devices with improved addressing capabilities, systems and methods | Physics | 10 | Expired |
| US5535348A | Block instruction | Physics | 9 | Expired |
| US6055628A | Microprocessor with a nestable delayed branch instruction without branch related pipeline interlocks | Physics | 9 | Expired |
| US5809309A | Processing devices with look-ahead instruction systems and methods | Physics | 8 | Expired |
| US5511146A | Excitory and inhibitory cellular automata for computational networks | Physics | 8 | Expired |
| US5841379A | Method and apparatus for selectively counting consecutive bits | Electricity | 8 | Expired |
| US5964825A | Manipulation of boolean values and conditional operation in a microprocessor | Physics | 8 | Expired |
| US6411984B1 | Processor integrated circuit | Physics | 7 | Expired |
| US5594914A | Method and apparatus for accessing multiple memory devices | Physics | 6 | Expired |
| US7039790B1 | Very long instruction word microprocessor with execution packet spanning two or more fetch packets with pre-dispatch instruction selection from two latches according to instruction bit | Physics | 5 | Expired |
| US6895494B1 | Sub-pipelined and pipelined execution in a VLIW | Physics | 3 | Expired |
| US11171651B2 | Mixed signal computer | Electricity | 0 | Active |
| US11347478B2 | Analog arithmetic unit | Physics | 0 | Active |
| US11373720B2 | Analog memory cells with valid flag | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.