System and method for processing a plurality of branch instructions by a plurality of storage devices and pipeline units
US6055630A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 20, 1998 |
| Grant date | Apr 25, 2000 |
| Priority date | — |
| Expiry date | Apr 20, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3867
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An instruction pipeline in a microprocessor is provided. The instruction pipeline includes a plurality of pipeline units, each of the pipeline units processing a plurality of instructions including branch instructions. The instruction pipeline further includes a plurality of storage device which store a respective branch information data. Each of the storage devices are associated with at least one of pipeline units. Each respective branch information data is determined as a function of at least one of the branch instructions processed. Two of the pipeline units include branch prediction circuitry for predicting branch direction as a function of the stored branch information data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.