Shallow trench isolation process using chemical-mechanical polish with self-aligned nitride mask on HDP-oxide

US6057207A · kind A · utility

Assignee

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. · TW

Inventors

• Chung-Te Lin · Tainan, TW
• Chin H. Ho · Sunnyvale, US

Key dates

• Filing date: Mar 25, 1998
• Grant date: May 2, 2000
• Expiry date: Mar 25, 2018

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76224
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method of planarizing a non-conformal oxide layer 40 forming shallow trench isolation between active areas 12 in a substrate. The invention uses a first chemical-mechanical polish (CMP) step to form openings 50 only over wide active areas. An etch is used to remove oxide 40 from only over the wide active areas 12A. A second CMP step is used to planarized the oxide layer 40. The invention begins by forming spaced trenches 30 in said substrate 10 defining active areas 12. A first insulating layer 40 composed of a non-conformal silicon oxide is formed by a HDPCVD process over the substrate and fills the trenches 30. A etch barrier layer 44 is formed over the first insulating layer 40. In a first chemical-mechanical polish (CMP) step, the conformal etch barrier layer 44 over only the wide raised portions 12A is polished to form a self-aligned first openings 50. The chemical-mechanical polishing of the conformal etch barrier layer forms a self-aligned etch mask. The first insulating layer 40 is then etched through at least the first opening 50 to expose a first barrier layer 24 over the wide active areas 12A. In a second CMP step, the etch barrier layer 44 is removed and the first ins…