Face on face flip chip integration
US6057598A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 31, 1997 |
| Grant date | May 2, 2000 |
| Priority date | — |
| Expiry date | Jan 31, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides methods and apparatus capable of efficiently combining a logic circuit die with a memory circuit die in a single integrated circuit device capable of supporting memory intensive applications, such as 3-dimensional graphics rendering, encryption and signal processing. The logic circuit die is produced independently with a logic circuit fabrication process that optimizes the logic circuit's performance and reduces costs, and the memory circuit die, which may contain a large memory circuit, can be produced independently with a memory circuit fabrication process that optimizes the memory circuit's performance and reduces costs. The circuit dies are attached directly together in a flip-chip fashion to create a unitary integrated circuit assembly having a high-performance, low impedance, wide-word interface. This integrated circuit assembly can be enclosed within a typical integrated circuit package for insertion on a circuit board, such as those used in personal computers and other common electronic applications.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.