Multi-bit-per-cell and analog/multi-level non-volatile memories with improved resolution and signal-to noise ratio
US6058060A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 31, 1998 |
| Grant date | May 2, 2000 |
| Priority date | — |
| Expiry date | Dec 31, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3418
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Applying a negative voltage to unselected word-lines during a read or verify operation reduces leakage current from over-erased memory cells, which allows the memory cells to be over-erased and therefore, to be programmed with lower threshold voltages. The consequence is a non-volatile memory having wider threshold voltage windows, which results in improved resolution and SNR for analog/multi-level and multi-bit-per-cell storage. During programming, the negative voltage is applied to word-lines containing unselected and erased memory cells in the same bit-line as the selected cell to prevent leakage current from over-erased cells, and a ground potential is applied to word-lines containing unselected and previously programmed cells in the selected bit-line to prevent drain disturb. In another embodiment, ground potential is applied to all the unselected word-lines during programming, which requires a programming load line and charge pump able to handle large currents and supply large voltages, respectively, due to the increased combined leakage current on the bit-line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.