Software-managed programmable unified/split caching mechanism for instructions and data
US6058456A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 14, 1997 |
| Grant date | May 2, 2000 |
| Priority date | — |
| Expiry date | Apr 14, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/601
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of allocating a cache used by a processor of a computer system between instructions and data is disclosed. Program instructions are loaded in the processor for monitoring relative usage of the cache by each value class and selecting a desired ratio of cache usage by the classes from among a plurality of available ratios, and cache blocks within the cache are evicted using a cache-replacement mechanism which restricts replacement of an evicted cache to a particular one of the classes of values (instruction or data) based on the desired ratio of cache usage. A multi-bit facility may be provided to indicate how to confine a selected victim to certain cache blocks, and the program instructions select the desired ratio of cache usage by setting the multi-bit facility. The cache-replacement mechanism can be a modified least recently used replacement mechanism. Different instruction/data ratios thereby may be provided, such as 1:1, 1:2, and 2:1.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.