Method of reducing computer module cycle time
US6058488A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 13, 1998 |
| Grant date | May 2, 2000 |
| Priority date | — |
| Expiry date | Feb 13, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L1/00
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A reduction of multichip module computer system cycle time is achieved by using a voltage regulator for power supply noise attenuation to reduce jitter. The circuit for doing this includes an active filter network circuit for use in the multichip module of a computer system which generates a quiet analog VDD coupled directly to ground by using the low impedance power supply distributions which already exist in the module. The active filter network permits taking the power supply voltage from the module and stepping it down to a voltage needed by a phased lock loop via an active filter, said active filter comprising an op-amplifier and a source follower and a large value on module capacitor for a resistor network. The capacitor and resistor network acts as a filter with a large time constant where noise appearing on VDD,MOD is completely attenuated by this high value capacitor and resistor network part of our active filter network.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.