Damascene NVRAM cell and method of manufacture
US6060358A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 21, 1997 |
| Grant date | May 9, 2000 |
| Priority date | — |
| Expiry date | Oct 21, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
Abstract
Recessing the floating gate of a NVRAM cell within a substrate or semiconductor layer between isolation structures permits manufacture by a simplified self-aligned process of high yield and economy while supporting maximum integration density and reducing or eliminating severe topography of the control gate connections which are formed in strips having a generally planar lower surface and which are of improved robustness and potentially fine pitch. Impurity implants are facilitated by thicknesses of various material present during portions of the process and in various combinations which may be advantageously exploited to obtain tailoring of impurity concentrations and profiles of both NVRAM cells and damascene field effect transistors formed by similar and compatible processes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.