Programmable clock manager for a programmable logic device that can be programmed without reconfiguring the device
US6060902A · kind A · utility
7Cited by
14References
16Claims
0Family size
Inventors
Key dates
| Filing date | Oct 15, 1997 |
| Grant date | May 9, 2000 |
| Priority date | — |
| Expiry date | Oct 15, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1774
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmable logic device (PLD), such as a field programmable gate array (FPGA), has a programmable clock manager (PCM) that converts an input clock into at least one output clock and the PCM can be programmed during PLD operations, without reconfiguring the PLD.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.