Databus
US6060908A · kind A · utility
4Cited by
2References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 4, 1998 |
| Grant date | May 9, 2000 |
| Priority date | — |
| Expiry date | Aug 4, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4213
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A databus includes n+1 (n.gtoreq.2) lines which form n true-only lines and lead from n input blocks to n output blocks. One of the true-only lines as well as a monitoring line are associated with one of the input blocks which is located at a start of the databus and has the longest signal delay time. A NAND gate is connected downstream of the input block at the start of the databus and has an output connected to each output block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.