Patrick Heyne
39Patents
9h-index
28Co-inventors
71Inventor score
Filing activity: Aug 4, 1998 → Sep 24, 2007
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6573754B2 | Circuit configuration for enabling a clock signal in a manner dependent on an enable signal | Electricity | 38 | Expired |
| US7414445B2 | Device and method for the synchronization of clock signals and adjustment of the duty cycle of the clock signal | Electricity | 25 | Active |
| US6194928A | Integrated circuit with adjustable delay unit | Electricity | 15 | Expired |
| US6259652A | Synchronous integrated memory | Physics | 15 | Expired |
| US6351167B1 | Integrated circuit with a phase locked loop | Electricity | 14 | Expired |
| US6584021B2 | Semiconductor memory having a delay locked loop | Physics | 13 | Expired |
| US6661265B2 | Delay locked loop for generating complementary clock signals | Electricity | 12 | Expired |
| US7404018B2 | Read latency control circuit | Physics | 9 | Active |
| US7016452B2 | Delay locked loop | Electricity | 9 | Expired |
| US6285228A | Integrated circuit for generating a phase-shifted output clock signal from a clock signal | Electricity | 8 | Expired |
| US6472921B1 | Delivering a fine delay stage for a delay locked loop | Electricity | 8 | Expired |
| US6285176A | Voltage generator with superimposed reference voltage and deactivation signals | Physics | 7 | Expired |
| US6737901B2 | Integrable, controllable delay device, delay device in a control loop, and method for delaying a clock signal using a delay device | Electricity | 6 | Expired |
| US6756820B1 | Optimized-delay multiplexer | Electricity | 6 | Expired |
| US6967893B2 | Integrated synchronous memory and memory configuration having a memory module with at least one synchronous memory | Physics | 6 | Expired |
| US6388944B2 | Memory component with short access time | Physics | 6 | Expired |
| US6366527B2 | Circuit configuration for generating an output clock signal with optimized signal generation time | Physics | 5 | Expired |
| US6670802B2 | Integrated circuit having a test operating mode and method for testing a multiplicity of such circuits | Physics | 5 | Expired |
| US6480024B2 | Circuit configuration for programming a delay in a signal path | Electricity | 5 | Expired |
| US6307416A | Integrated circuit for producing two output clock signals at levels which do not overlap in time | Electricity | 4 | Expired |
| US6060908A | Databus | Physics | 4 | Expired |
| US6198328A | Circuit configuration for producing complementary signals | Electricity | 4 | Expired |
| US6469563B2 | Circuit configuration for compensating runtime and pulse-duty-factor differences between two input signals | Electricity | 3 | Expired |
| US6125066A | Circuit configuration and method for automatic recognition and elimination of word line/bit line short circuits | Physics | 3 | Expired |
| US6532188B2 | Integrated memory having a row access controller for activating and deactivating row lines | Physics | 3 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.