PLL response time accelerating system using a frequency detector counter
US6060953A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 8, 1998 |
| Grant date | May 9, 2000 |
| Priority date | — |
| Expiry date | Apr 8, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/181
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A PLL response time is accelerated with a frequency detector counter. The PLL utilizes both a phase frequency detector and the frequency detector counter. Initially, the operation of the PLL is controlled by the frequency detector counter and the output of phase frequency detector does not affect the PLL system. During this period, the PLL synchronizes to an input clock frequency. After the PLL reaches a predetermined frequency range, the frequency detector counter stops working. Thereafter, the phase frequency detector controls the operation of the PLL. During this period, the PLL synchronizes to both the frequency and the phase of the input signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.