Execution unit chaining for single cycle extract instruction having one serial shift left and one serial shift right execution units
US6061780A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 23, 1998 |
| Grant date | May 9, 2000 |
| Priority date | — |
| Expiry date | Jan 23, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3853
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A VLIW microprocessor capable of executing two or more instructions having data dependency in a single cycle. The microprocessor includes an instruction fetch and decode unit, a register file, and a plurality of execution units communicating with the instruction fetch and decode unit and with the register file. At least two of the execution units are connected such that the output of a first one of the two execution units is connected to the input of a second one of the two execution units, such that the output of the first execution unit is available as an input to the second execution unit during said single cycle, and such that both execution units can execute in said single cycle. In an exemplary embodiment, the first execution unit is a shift left unit, and the second execution unit is a shift right unit. With this embodiment, a complete extract operation can be performed in a single cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.