Concurrent execution of divide microinstructions in floating point unit and overflow detection microinstructions in integer unit for integer divide
US6061781A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 1, 1998 |
| Grant date | May 9, 2000 |
| Priority date | — |
| Expiry date | Jul 1, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/4991
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for performing integer division in a microprocessor are provided. The apparatus includes translation logic, floating point execution logic, and integer execution logic. The translation logic decodes an integer divide instruction into an integer divide micro instruction sequence and an overflow detection micro instruction sequence. The integer divide micro instruction sequence is routed to and executed by the floating point execution logic. The overflow detection micro instruction sequence is routed to and executed by the integer execution logic. The integer execution logic and the floating point execution logic execute the overflow detection micro instruction sequence and the integer divide micro instruction sequence concurrently.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.