Gate fabrication processes for split-gate transistors
US6063670A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 15, 1998 |
| Grant date | May 16, 2000 |
| Priority date | — |
| Expiry date | Apr 15, 2018 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/911
Abstract
A method for forming an integrated circuit having multiple gate oxide thicknesses is disclosed herein. The circuit (10) is processed up to gate oxide formation. A first gate dielectric (20) is formed. Next, a disposable layer (22) is formed over the first gate dielectric (20). The disposable layer (22) comprises a material that may be removed selectively with respect to silicon and the gate dielectric, such as germanium. If desired, a second dielectric layer (24) may be formed over the disposable layer (22). A pattern (26) is then formed exposing areas (14) of the circuit where a thinner gate dielectric is desired. The second dielectric layer (24), if it is present, and the disposable layer (22) are removed from the exposed areas. The pattern (26) is then removed. Following pre-gate cleaning, the second gate dielectric (30) is formed. The remaining portions of the disposable layer (22) may be removed either prior to, during, or after the second gate dielectric formation (30).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.