Fabrication of deep submicron structures and quantum wire transistors using hard-mask transistor width definition
US6063688A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 29, 1997 |
| Grant date | May 16, 2000 |
| Priority date | — |
| Expiry date | Sep 29, 2017 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/947
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The invention relates to a method of forming reduced feature size spacers. The method includes providing a semiconductor substrate having an area region; patterning a first spacer over a portion of the area region of the substrate, the first spacer having a first thickness and opposing side portions; patterning a pair of second spacers, each second spacer adjacent to a side portion of the first spacer, each second spacer having a second thickness in opposing side portions, wherein the second thickness is less than the first thickness; removing the first spacer; patterning a plurality of third spacers, each third spacer adjacent to one of the side portions of one of the second spacers, each one of the third spacers having a third thickness, wherein the third thickness is less than the second thickness; and removing the second spacers. The invention also relates to a field of effect transistor. The transistor includes a semiconductor substrate having a source region and a drain region; a gate area of the substrate surface; a channel region in the substrate having a cross-sectional area defined by a portion of the gate area, a channel length measured accross a portion of the channel r…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.