Substrate for holding a chip of semi-conductor package, semi-conductor package, and fabrication process of semi-conductor package
US6064111A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Jul 31, 1997 |
| Grant date | May 16, 2000 |
| Priority date | — |
| Expiry date | Jul 31, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor packaging chip-supporting substrate of the present invention comprises an insulating supporting substrate, wiring provided on the substrate, and an insulating film provided on the wiring. The wiring each have i) an inner connection that connects to a semiconductor chip electrode and ii) a semiconductor chip-mounting region. An opening is also provided in the insulating supporting a substrate at its part where each of the wiring is formed on the insulating supporting substrate, which is the part where an outer connection conducting to the inner connection is provided. The insulating film is formed at the part on which the semiconductor chip is mounted, covering the semiconductor chip-mounting region of the wiring.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.