CMOS input buffer protection circuit
US6064231A · kind A · utility
11Cited by
4References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 28, 1998 |
| Grant date | May 16, 2000 |
| Priority date | — |
| Expiry date | Apr 28, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2217/0018
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A low voltage CMOS input buffer protection circuit that is used to protect an input buffer from any high voltage signal (e.g., 5 V) that may appear along a signal bus. The protection circuit is also "hot-pluggable", meaning that the protection circuit will not draw any current when not powered (i.e., when VDD is not present). The circuit includes a CMOS transmission gate and utilizes on-chip generated reference voltages to provide the necessary protection.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.