Lateral DMOS design for ESD protection

US6064249A · kind A · utility

Assignee

• TEXAS INSTRUMENTS INCORPORATED · US

Inventors

• Charvaka Duvvury · Plano, US
• Fred Carvajal · Fairview, US
• David D. Briggs · Richardson, US

Key dates

• Filing date: Jun 17, 1998
• Grant date: May 16, 2000
• Expiry date: Jun 17, 2018

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D89/911

Abstract

A LDMOS having improved ESD reliability and a method for designing such a LDMOS. A higher gate clamp voltage and/or minimized drain clamp voltage is used to maximize the ESD performance of the LDMOS. Given a set of design parameters, one or more of the gate clamp voltage, drain clamp voltage, or size of the LDMOS are optimized to meet the design parameters while achieving the optimum ESD performance.