Cover instruction and asynchronous backing store switch
US6065114A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 21, 1998 |
| Grant date | May 16, 2000 |
| Priority date | — |
| Expiry date | Apr 21, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/461
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer-implemented method of switching contexts in a processor is provided. The processor includes a register stack (RS) that has first and second portions. The processor includes a register stack engine (RSE) to exchange information, in one of instruction execution dependent and independent modes between the second portion and the storage area. The computer implemented method of switching contexts includes the following steps: It is determined whether an interrupt occurred; a first register (IFM) configured to store a content of a second register (CFM) is invalidated, the CFM is configured to store control information related to the first portion; it is determined whether an interrupt handler needs to access the RS; and if so, the IFM is validated, the content of the CFM is copied to the IFM, and RSE is caused to exchange information between both the first and second portions of the RS and the storage area. On return from interruption, if IFM is validated, CFM is restored from IFM else CFM remains unchanged. The COVER instruction enables lightweight interrupt handling in a processor with a Register Stack.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.