Apparatus and method for electrical determination of delamination at one or more interfaces within a semiconductor wafer
US6066561A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 19, 1997 |
| Grant date | May 23, 2000 |
| Priority date | — |
| Expiry date | Dec 19, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/12
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An apparatus and method are presented for electrically determining whether delamination has occurred at one or more interfaces within a semiconductor wafer. The semiconductor wafer includes a test structure formed within dielectric layers upon an upper surface of a semiconductor substrate. The test structure includes an electrically conductive structure, a pair of electrically conductive contact plugs, and a probe pad. The conductive structure is formed within an opening in a first dielectric layer, and is in electrical contact with the upper surface of the semiconductor substrate. The conductive structure is preferably made up of the same vertical stack of layers of selected electrically conductive materials used to form interconnects within the semiconductor wafer. A second dielectric layer if formed over the first dielectric layer and the conductive structure. The pair of electrically conductive contact plugs extend vertically through respective holes in the second dielectric layer. An electrically conductive probe pad is formed upon an upper surface of the second dielectric layer and extends between the pair of contact plugs. Each contact plug is in electrical contact with the …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.