Semiconductor device testing apparatus and semiconductor device testing system having a plurality of semiconductor device testing apparatus
US6066822A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 27, 1997 |
| Grant date | May 23, 2000 |
| Priority date | — |
| Expiry date | Mar 27, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31912
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A semiconductor device testing system is provided efficiently utilizes a plurality of semiconductor device testing apparatus. More particularly, a host computer controls a plurality of semiconductor device testing apparatuses and a dedicated classifying machine. A storage information memory stores storage information of each semiconductor device such as a number assigned to each tested semiconductor device such as a number assigned to each tested semiconductor device, the test results of each semiconductor device, and is provided in the host computer. Without sorting the tested devices or with the sorting operation of the tested devices into only two categories in a handler part of each testing apparatus, the tested devices are transferred from the test tray to a general-purpose tray, and during this transfer operation, the storage information of each device is stored in the storage information memory. When all of the tests are completed, the storage information of each device stored in the storage information memory is transmitted to the dedicated classifying machine by which the tested devices are sorted out.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.