Single layer integrated metal enhancement mode field-effect transistor apparatus
US6066865A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 14, 1998 |
| Grant date | May 23, 2000 |
| Priority date | — |
| Expiry date | Apr 14, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/877
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An enhancement mode periodic table group III-IV semiconductor field-effect transistor device is disclosed. The disclosed transistor includes single metallization for ohmic and Schottky barrier contacts, a permanent non photosensitive passivation layer (a layer which has also been used for masking purposes during fabrication of the transistor) and a gate element of small dimension and shaped cross section as needed to provide desirable microwave spectrum electrical characteristics. The transistor of the invention is fabricated from undoped semiconductor materials disposed in a layered wafer structure and selectively doped by ion implantation to achieve either a p-channel or an n-channel transistor. The semiconductor materials may include two, one or zero buffer layers in their layer structure. The disclosed transistor is of reduced fabrication cost, increased dimensional accuracy and state of the art electrical performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.